1. Field of the Invention
The present invention relates to a PLL frequency synthesizer, and particularly to a PLL frequency synthesizer capable of achieving an improvement in spurious characteristic in a steady state while maintaining a high-speed lockup characteristic.
2. Description of the Related Art
In mobile communications for cellular telephones or the like which have widely been available in recent years, communications are made based on a carrier frequency corresponding to a predetermined frequency. In order to ensure communication quality and satisfactorily keep a C/N (Carrier to Noise) characteristic in the communications at this time, there is a need to accurately lock a predetermined carrier frequency, and hence a PLL frequency synthesizer has been used. The operation of locking the carrier frequency by the PLL frequency synthesizer is needed not only during a communication period but also during a so-called standby period corresponding to a state of waiting for reception from the party on the other end of the communication. That's why it needs to always detect the presence or absence of a communication access from the communication party and immediately establish communications when the access is received. On the other hand, a mobile communications apparatus such as a cellular phone or the like needs to reduce its current consumption to the minimum according to its portability. Thus, in the apparatuses used under the present conditions in order to implement a standby or awaiting operation while current consumption is being suppressed, a PLL frequency synthesizer is intermittently operated only during a predetermined period set for each predetermined cycle to carry out an intermittent operation for locking a carrier frequency and performing the standby operation, thereby coping with it. With a view toward promptly carrying out a repeated operation of lock and stop operations at a carrier frequency for each predetermined cycle or period, it is necessary to make a lockup characteristic of the PLL frequency synthesizer faster and set low the time constant of a low-pass filter circuit.
FIG. 11 shows a PLL frequency synthesizer 100 according to a prior art. A phase comparator 101 receives therein a reference frequency signal fr and an output frequency signal fp outputted from a voltage-controlled oscillator (VCO) 104. Then the phase comparator 101 outputs phase difference signals Pr and Pp each corresponding to the difference in phase between the reference frequency signal fr and the output frequency signal fp. A charge pump circuit 102 receives these signals therein and outputs a voltage output signal Do. A low-pass filter (LPF) circuit 103 eliminates AC components of the voltage output signal Do and makes adjustments around the phase to ensure the stability of a system. Besides, the low-pass filter (LPF) circuit 103 outputs a control voltage signal Vt to the voltage-controlled oscillator (VCO) 104. Then the voltage-controlled oscillator (VCO) 104 outputs the output frequency signal fp corresponding to the control voltage signal Vt. The PLL frequency synthesizer 100 forms a feedback loop which returns from the phase comparator 101 to the phase comparator 101 via the charge pump circuit 102, the low-pass filter (LPF) circuit 103 and the voltage control oscillator (VCO) 104. The phase difference signals Pr and Pp, which cancel out the phase difference between the reference frequency signal fr and the output frequency signal fp compared with the reference frequency signal fr are outputted from the charge pump circuit 102 and fed back to the voltage controlled-oscillator (VCO) 104 as the control voltage signal Vt through the low-pass filter (LPF) circuit 103. If the frequency of the output frequency signal fp coincides with that of the reference frequency signal fr, then no phase difference signals Pr and Pp are outputted and the output frequency signal fp is locked to the same frequency as that of the reference frequency signal fr. In order to make faster a lockup time of the low-pass filter (LPF) circuit 103 here, there is a need to set low the time constant of the low-pass filter (LPF) circuit 103.
Japanese Patent Application Laid-Open No. Hei 10(1998)-51299 has described a PLL frequency synthesizer circuit including a PLL synthesizer IC using phase-locked loop, a low-pass filter LPF which converts the output of the IC to a DC voltage, and a voltage-controlled oscillator VCO which outputs a frequency corresponding to a control voltage, wherein switching means for separating the output of a phase comparator of the PLL synthesizer IC from the LPF prior to timing provided to turn ON/OFF a source or power supply for a load circuit, and connecting the output of the phase comparator of the PLL synthesizer IC to the LPF again is provided.
Japanese Patent Application Laid-Open No. Hei 5(1993)-183432 has described a clock reproducing circuit having a voltage-controlled oscillator which generates an output signal varied in frequency according to an input control signal, a phase comparator which compares the phase of an intermittently applied input signal and that of the output signal of the voltage-controlled oscillator and sends out its corresponding phase difference signal, and a first low-pass filter unit which eliminates unnecessary components in the phase difference signal, wherein a second low-pass filter unit which takes out a component corresponding to the difference between the frequency of the input signal and the free-running frequency of the voltage-controlled oscillator, and switch/adding means which sends out a signal as the control signal obtained by adding the output of the first low-pass filter unit and the output of the second low-pass filter unit when the input signal is applied, and sends out the output of the second low-pass filter unit as the control signal when no input signal is applied, are added thereto.
When the frequency of the output frequency signal fp is locked to the same frequency as the reference frequency signal fr by the aforementioned PLL frequency synthesizer 100, the phase difference signals Pr and Pp of the phase comparator 101 are not outputted as the average. Even in this state, however, a phase correction pulse having the same amounts of positive and negative energy is outputted to the voltage output signal Do produced from the charge pump circuit 102 during an output period of the reference frequency signal fr corresponding to a phase comparison period in the phase comparator 101 as shown in FIG. 12 (hereinafter called “pseudo correction pulse”). While the present pulse can be eliminated by adjusting the time constant of the low-pass filter (LPF) circuit 103, it has a trade-off relationship with a lockup characteristic. Namely, if the time constant of the low-pass filter (LPF) circuit 103 is set high, then the pseudo correction pulse in the voltage output signal Do can be masked but a lockup time becomes long. Thus, this does not match the demand for a high-speed lockup characteristic, thereby causing a problem. If the time constant of the low-pass filter (LPF) circuit 103 is set low in reverse, then the demand for the high-speed lockup characteristic can be satisfied but the pseudo correction pulse in the voltage output signal Do cannot be masked. Thus, spurious outputs are developed, so that C/N is degraded and communication quality cannot be ensured, thereby causing a problem. The prior art is accompanied by a problem due to the possibility that the time constant should unavoidably be adjusted at a compromise between both characteristics, and the optimum operating state cannot be implemented where further speeding-up ahead is viewed.
A description will now be made of the reason why the pseudo correction pulse in the voltage output signal Do is developed. FIG. 13 shows an input/output characteristic of the charge pump circuit 102. The charge pump circuit 102 is a circuit which outputs a voltage output signal Do proportional to each of input phase difference signals Δφ (Pr and Pp in FIG. 11). The phase difference signal Δφ at this time takes a phase delay of the output frequency signal fp with respect to the reference frequency signal fr as positive. Thus, when the phase of the output frequency signal fp is delayed and a positive phase difference signal Δφ is inputted, a positive voltage output signal Do is outputted and inputted to the voltage-controlled oscillator (VCO) 104 through the low-pass filter (LPF) circuit 103, where the phase of the output frequency signal fp is advanced, whereby the output frequency signal fp approaches the reference frequency signal fr so as to lock. When the phase of the output frequency signal fp leads and a negative phase difference signal Δφ is inputted in reverse, a negative voltage output signal Do is outputted and inputted to the voltage-controlled oscillator (VCO) 104 through the low-pass filter (LPF) circuit 103, where the phase of the output frequency signal fp is delayed, whereby the output frequency signal fp approaches the reference frequency signal fr so as to lock. Ideally, the phase difference signals Δφ and the voltage output signal Do need to have a linear relation (see characteristic straight line L0 in FIG. 13). In the actual charge pump circuit 102, however, the relationship between the phase difference signals Δφ and the voltage output signal Do in a small phase-difference region X becomes non-linear due to the time of a delay in finite signal propagation time of the circuit (see regions D in characteristic curves L0D in FIG. 13) and hence no voltage output signal Do is outputted. This small phase-difference region X is called a dead or blind zone. Thus, in order to solve the dead zonal region X, the actual charge pump circuit 102 is generally configured so as to have nonlinear characteristics obtained by shifting the characteristics of the phase difference signals Δφ and the voltage output signal Do in the direction to decrease gain as viewed from the linear characteristic in the dead zonal region X (see characteristic curves L in FIG. 13). Owing to the provision of such characteristic curves L, the voltage output signal Do relative to the phase difference signals Δφ has finite gain even in the minute phase-difference region X, and hence a phase correction pulse is outputted.
Japanese Patent Application Laid-Open No. Hei 10(1998)-51299 aims to prevent the occurrence of a variation in frequency due to the turning ON/OFF of a power source or supply for a load circuit and transmit or receive data immediately after the power source is connected to the load circuit. However, the present publication does not disclose a technical idea wherein spurious generation in a steady state of the PLL frequency synthesizer circuit is suppressed while the time constant of the low-pass filter LPF is being reduced low and a high-speed lockup characteristic is being improved. Thus, a problem arises in that a trade-off relation between the two cannot be solved and both the high-speed lockup characteristic and a low spurious characteristic at the steady time cannot be realized.
Japanese Patent Application Laid-Open No. Hei 5(1993)-183432 aims to always supply a proper reproduced clock even when a receiver is shifted from as top state to an operating state. However, the present publication does not show a technical idea wherein spurious generation in a steady state is suppressed while the time constant of the first low-pass filter unit is being reduced low and a high-speed lockup characteristic is being improved. Thus, a problem arises in that a trade-off relation between the two cannot be solved and both the high-speed lockup characteristic and a low spurious characteristic at the steady time cannot be realized.